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74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
Rev. 06 -- 13 November 2008 Product data sheet
1. General description
The 74LVT16244B; 74LVTH16244B is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is a 16-bit buffer and line driver featuring non-inverting 3-state bus outputs. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
2. Features
I I I I I I I I I I 16-bit bus interface 3-state buffers Output capability: +64 mA and -32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Power-up 3-state Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Latch-up protection N JESD78 Class II exceeds 500 mA I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information Package Temperature range 74LVT16244BDL 74LVTH16244BDL 74LVT16244BDGG 74LVTH16244BDGG 74LVT16244BEV 74LVT16244BBQ 74LVTH16244BBQ -40 C to +85 C -40 C to +125 C VFBGA56 -40 C to +85 C TSSOP48 -40 C to +85 C Name SSOP48 Description plastic shrink small outline package; 48 leads; body width 7.5 mm plastic thin shrink small outline package; 48 leads; body width 6.1 mm plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm Version SOT370-1 SOT362-1 SOT702-1 SOT1025-1 Type number
HUQFN60U plastic thermal enhanced ultra thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.55 mm
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
4. Functional diagram
1 1OE 48 2OE 25 3OE 24 4OE 1A0 1A1 17 1A2 1A3 1 1OE 25 2Y0 3OE 2A0 2A1 41 40 2A0 8 9 30 29 4A0 4Y0 19 20 2A2 2A3 2A1 2Y1 4A1 4Y1 3A0 3A1 38 2A2 2Y2 11 27 4A2 4Y2 22 3A2 3A3 4A0 23 4A1 4A2 4A3
001aae506
47 46
1A0
1Y0
2 3
36 35
3A0
3Y0
13 14
1A1
1Y1
3A1
3Y1
EN1 EN2 EN3 EN4 1 1 2 3 5 6 1 2 8 9 11 12 1 3 13 14 16 17 1 4 19 20 22 23 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3
44
1A2
1Y2
5
33
3A2
3Y2
16
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
43
1A3
1Y3
6
32
3A3
3Y3
37
2A3 2OE
2Y3
12
26
4A3 4OE
4Y3
48
24
001aae231
Pin numbers are shown for SSOP48 and TSSOP48 packages only.
Pin numbers are shown for SSOP48 and TSSOP48 packages only.
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
2 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
5. Pinning information
5.1 Pinning
74LVT16244B 74LVTH16244B
1OE 1Y0 1Y1 GND 1Y2 1Y3 VCC 2Y0 2Y1 1 2 3 4 5 6 7 8 9 48 2OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 2A0 40 2A1 39 GND 38 2A2 37 2A3 36 3A0 35 3A1 34 GND 33 3A2 32 3A3 31 VCC 30 4A0 29 4A1 28 GND 27 4A2 26 4A3 25 3OE
001aae507
GND 10 2Y2 11 2Y3 12 3Y0 13 3Y1 14 GND 15 3Y2 16 3Y3 17 VCC 18 4Y0 19 4Y1 20 GND 21 4Y2 22 4Y3 23 4OE 24
74LVT16244B
ball A1 74LVTH16244B index area 123456 A B C D E F G H J K
001aaj057
Transparent top view
Fig 3.
Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
Fig 4.
Pin configuration SOT702-1 (VFBGA56)
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
3 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
terminal 1 index area
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 GND(1) B11 B12 B13 B15 B16 B17
A25
A24
A23
A22
74LVT16244B 74LVTH16244B
B14 A21
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aaj056
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 5.
Pin configuration SOT1025-1 (HUQFN60U)
5.2 Pin description
Table 2. Symbol Pin description Pin SOT370-1 and SOT362-1 1OE, 2OE, 3OE, 4OE 1, 48, 25, 24 SOT702-1 A1, A6, K6, K1 B2, B1, C2, C1 D2, D1, E2, E1 F1, F2, G1, G2 H1, H2, J1, J2 SOT1025-1 A30, A29, A14, A13 B20, A31, D5, D1 A2, B2, B3, A5 A6, B5, B6, A9 D2, D6, A12, B8 output enable input (active LOW) data output data output data output data output Description
1Y0 to 1Y3 2, 3, 5, 6 2Y0 to 2Y3 8, 9, 11, 12 3Y0 to 3Y3 13, 14, 16, 17 4Y0 to 4Y3 19, 20, 22, 23
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
4 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
Table 2. Symbol
Pin description ...continued Pin SOT370-1 and SOT362-1 SOT702-1 B3, B4, D3, D4, G3, G4, J3, J4 C3, C4, H3, H4 B5, B6, C5, C6 D5, D6, E5, E6 F6, F5, G6, G5 H6, H5, J6, J5 A2, A3, A4, A5, K2, K3, K4, K5 SOT1025-1 A32, A3, A8, A11, A16, A19, A24, A27 A1, A10, A17, A26 B18, A28, D8, D4 A25, B16, B15, A22 A21, B13, B12, A18 D3, D7, A15, B10 A4, A7, A20, A23, B1, B4, B7, B9, B11, B14, B17, B19 ground (0 V) supply voltage data input data input data input data input not connected Description
GND VCC
4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42
1A0 to 1A3 47, 46, 44, 43 2A0 to 2A3 41, 40, 38, 37 3A0 to 3A3 36, 35, 33, 32 4A0 to 4A3 30, 29, 27, 26 n.c. -
6. Functional description
Table 3. Control nOE L L H
[1]
Function table[1] Input nAn L H X Output nYn L H Z
H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state.
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO Tstg Tj Parameter supply voltage input voltage output voltage input clamping current output clamping current output current storage temperature junction temperature
[2] [1]
Conditions
Min -0.5 -0.5 -0.5 -50 -50 -64 -65 -
Max +4.6 +7.0 +7.0 128 +150 150
Unit V V V mA mA mA mA C C
output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state output in HIGH-state
[1]
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
5 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
Table 4. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Ptot Parameter total power dissipation Conditions Tamb = -40 C to +125 C; (T)SSOP48 package VFBGA56 package HUQFN60U package
[1] [2] [3] [4]
[3] [4] [4]
Min -
Max 500 1000 1000
Unit mW mW mW
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. Above 60 C the value of Ptot derates linearly with 5.5 mW/K. Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5. Symbol VCC VI VIH VIL IOH IOL Recommended operating conditions Parameter supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current none current duty cycle 50 %; fi 1 kHz Tamb t/V ambient temperature in free-air input transition rise and fall rate outputs enabled Conditions Min 2.7 0 2.0 -32 -40 Typ Max 3.6 5.5 0.8 32 64 +85 10 Unit V V V V mA mA mA C ns/V
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
6 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +85 VIK VOH C[1] VCC = 2.7 V; IIK = -18 mA IOH = -8 mA; VCC = 2.7 V IOH = -32 mA; VCC = 3.0 V VOL LOW-level output voltage VCC = 2.7 V IOL = 100 A IOL = 24 mA VCC = 3.0 V IOL = 16 mA IOL = 32 mA IOL = 64 mA II input leakage current all input pins; VCC = 0 V or 3.6 V; VI = 5.5 V control pins; VCC = 3.6 V; VI = VCC or GND data pins; VCC = 3.6 V VI = VCC VI = 0 V IOFF IBHL IBHH IBHLO IBHHO IHOLD power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current bus hold current data input VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V nAn input; VCC = 0 V to 3.6 V; VI = 3.6 V nAn input; VCC = 0 V to 3.6 V; VI = 3.6 V VCC = 3 V VI = 0.8 V VI = 2.0 V VCC = 0 V to 3.6 V VI = 3.6 V ILO IO(pu/pd) IOZ output leakage current power-up/power-down output current OFF-state output current output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don't care VCC = 3.6 V; VI = VIH or VIL output HIGH: VO = 3.0 V output LOW: VO = 0.5 V 0.5 +0.5 5 -5 A A
[4] [3] [3] [2]
Conditions
Min -1.2 2.4 2.0 75 - 500 -
Typ -0.85 2.5 2.3 0.07 0.3 0.25 0.3 0.4 0.4 0.1 0.1 -0.4 0.1 135 -135 -
Max 0.2 0.5 0.4 0.5 0.55 10 1.0 1 -5 100 -75 -500
Unit V V V V V V V V V A A A A A A A A A
input clamping voltage
HIGH-level output voltage IOH = -100 A; VCC = 2.7 V to 3.6 V
VCC - 0.2 VCC
75 500 -
135 -135 50 1
-75 125 100
A A A A A
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
7 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC supply current Conditions VCC = 3.6 V; VI = GND or VCC; IO = 0 A output HIGH output LOW outputs disabled ICC CI CO
[1] [2] [3] [4] [5] [6]
[5] [6]
Min -
Typ 0.07 4.0 0.07 0.1 3 9
Max 0.12 6.0 0.12 0.2 -
Unit mA mA mA mA pF pF
additional supply current input capacitance output capacitance
per input pin; VCC = 3.0 V to 3.6 V; one input at VCC - 0.6 V other inputs at VCC or GND VI = 0 V or 3.0 V outputs disabled; VO = 0 V or 3.0 V
Typical values are measured at VCC = 3.3 V and at Tamb = 25 C. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol tPLH Parameter C[1] nAn to nYn; see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHL HIGH-to-LOW propagation delay nAn to nYn; see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPZH OFF-state to HIGH propagation delay nOE to nYn; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPZL OFF-state to LOW propagation delay nOE to nYn; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHZ HIGH to OFF-state propagation delay nOE to nYn; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPLZ LOW to OFF-state propagation delay nOE to nYn; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V
[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 C.
(c) NXP B.V. 2008. All rights reserved.
Conditions
Min
Typ
Max
Unit
Tamb = -40 C to +85
LOW-to-HIGH propagation delay
0.5 0.5 1.0 1.0 1.0 1.0
1.8 1.7 2.3 2.1 3.2 2.9
4.0 3.2 4.0 3.2 5.0 4.0 5.3 4.0 5.0 4.5 4.4 4.0
ns ns ns ns ns ns ns ns ns ns ns ns
74LVT_LVTH16244B_6
Product data sheet
Rev. 06 -- 13 November 2008
8 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
11. Waveforms
VI nAn input GND tPLH VOH nYn output VOL VM VM
mna171
VM
VM
tPHL
Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Propagation delay input (nAn) to output (nYn)
VI nOE input GND tPZL 3.0 V nYn output VOL
t PZH t PHZ
VM
tPLZ
VM
VX
VOH nYn output 0V
001aae464
VM
VY
Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Table 8. Input VM 1.5 V
3-state output enable and disable times Measurement points Output VM 1.5 V VX VOL + 0.3 V VY VOH - 0.3 V
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
9 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM
VI positive pulse 0V
VEXT VCC PULSE GENERATOR VI DUT
RT CL RL RL
VO
001aae235
Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.
Fig 8. Table 9. Input VI 2.7 V
Load circuit for measuring switching times Test data Load fi 10 MHz tW 500 ns tr, tf 2.5 ns CL 50 pF RL 500 VEXT tPHZ, tPZH GND tPLZ, tPZL 6V tPLH, tPHL open
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
10 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
D
E
A X
c y HE vM A
Z 48 25
Q A2 A1 (A 3) Lp 1 bp 24 wM L detail X A
pin 1 index
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 9. Package outline SOT370-1 (SSOP48)
74LVT_LVTH16244B_6 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
11 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT362-1 (TSSOP48)
74LVT_LVTH16244B_6 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
12 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
SOT702-1
D
B
A
ball A1 index area
E
A
A2 A1
detail X
e1 e
1/2 e
b
v M C A B w M C
C y1 C y
K J H e G F E D C B A ball A1 index area 1 2 3 4 5 6
1/2 e
e2
X
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.3 0.2 A2 0.7 0.6 b 0.45 0.35 D 4.6 4.4 E 7.1 6.9 e 0.65 e1 3.25 e2 5.85 v 0.15 w 0.08 y 0.08 y1 0.1 0 2.5 scale 5 mm
OUTLINE VERSION SOT702-1
REFERENCES IEC JEDEC MO-225 JEITA
EUROPEAN PROJECTION
ISSUE DATE 02-08-08 03-07-01
Fig 11. Package outline SOT702-1 (VFBGA56)
74LVT_LVTH16244B_6 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
13 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
HUQFN60U: plastic thermal enhanced ultra thin quad flat package; no leads 60 terminals; UTLP based; body 4 x 6 x 0.55 mm
D B A
SOT1025-1
terminal 1 index area
E
A
A1
detail X
e2 v w
M M
CAB C e
e1 1/2 e
b
v w
M M
CAB C C
L1 L eR
D2 D6
A11
B8
B10
A16
D3 D7
y1 C
y
A10 B7
A17 B11
e
Eh 1/2 e
B1 A1 B17 A26
e3
e4
terminal 1 index area
D5 D1
A32
B20
B18
A27
Dh
D8 D4
k
X 0 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.6 A1 0.05 0.00 b 0.35 0.25 D 4.1 3.9 Dh 1.9 1.8 E 6.1 5.9 Eh 3.9 3.8 e 0.5 e1 1 e2 2.5 e3 3
e4 4.5
eR 0.5
k 0.25 0.15
L
L1
v
w 0.05
y 0.08
y1 0.1
0.35 0.125 0.07 0.25 0.025 EUROPEAN PROJECTION
OUTLINE VERSION SOT1025-1
REFERENCES IEC --JEDEC --JEITA ---
ISSUE DATE 07-08-28 07-11-14
Fig 12. Package outline SOT1025-1 (HUQFN60U)
74LVT_LVTH16244B_6 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
14 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
13. Abbreviations
Table 10. Acronym BiCMOS DUT ESD HBM MM TTL Abbreviations Description Bipolar Complementary Metal Oxide Semiconductor Device Under Test Electrostatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
14. Revision history
Table 11. Revision history Release date 20081113 Data sheet status Product data sheet Change notice Supersedes 74LVT_LVTH16244B_5 Document ID 74LVT_LVTH16244B_6 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74LVT16244BBQ and 74LVTH16244BBQ (HUQFN60U package) Product data sheet Product specification Product specification Product specification 74LVT16244B_4 74LVT16244B_3 74LVT16244B_2 -
74LVT_LVTH16244B_5 74LVT16244B_4 74LVT16244B_3 74LVT16244B_2
20060321 20021031 19981007 19980219
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
15 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVT_LVTH16244B_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 November 2008
16 of 17
NXP Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2008 Document identifier: 74LVT_LVTH16244B_6

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